The present invention relates to a capacitor of a semiconductor memory device and a manufacturing method thereof, and more particularly to a dynamic random access memory (DRAM) device having a greatly increased cell capacitance by means of an advantageously simple manufacturing process, and a manufacturing method of the same.
A DRAM has a plurality of memory cells, each of which generally includes a storage capacitor and a transistor serving as a transfer gate for storing or eliminating charges. The plurality of memory cells are arranged on a substrate in a matrix arrangement and operate to permit only a single cell in the memory to be selected by means of two dimensional addressing within a given time period. A bit line (data line) voltage is supplied to the storage capacitor via a transistor so as to write information on each memory cell. Also, in order to read out the written information, the storage capacitor is connected to the data line via a gate and the voltage of the storage capacitor is thus monitored.
Meanwhile, with the development of semiconductor manufacturing techniques, the memory capacitance (number of elements per chip) in semiconductor memory devices is being increased as much as fourfold every two years. In such a memory device, since the memory cell array occupies a greater part of the chip area, each unit memory cell area must be shrunk to achieve larger capacitance and higher packing density, based upon the proportional reduction rule. However, a decrease of the memory cell area necessarily results in a decrease of the capacity of a stored change which should be stored within a minute memory cell for data storage.
This decrease of capacitance lowers the data read-out capability of the device and, because of .alpha.-particles, raises its soft error rate. It also impedes low voltage operation which consumes excessive electric power. Therefore, these problems must be solved before higher packing density of a semiconductor device can be achieved.
Generally, to increase the capacitance within a limited area, methods to increase the surface area of a capacitor's storage electrodes are being explored, as is decreasing the thickness of a dielectric film of the capacitor or increasing dielectric constant of the dielectric film etc. Among these, proposed structures for increasing the surface area of the storage electrode include a stacked capacitor, a trenched capacitor, and a combined capacitor. Here, since the stacked capacitor is simple in view of its manufacturing process as compared with the trenched capacitor and more immune to soft errors, studies on the stacked capacitor are being carried out in megabit-DRAMs.
On the other hand, sufficient capacitance cannot be obtained by a conventional two-dimensional stacked capacitor in 64 Mbit DRAMs which are generally restricted to a memory cell area of about 1.about.1.5 .mu.m.sup.2 even though a high-dielectric material, e.g., Ta.sub.2 O.sub.5, is used. Stacked capacitors having a three-dimensional structure have been therefore suggested. For example, the double-stacked structure, fin structure, cylindrical electrode structure, spread-stacked structure, and box structure are three-dimensional storage electrodes suggested to increase the cell capacitance of the memory cell.
Among the above three-dimensional stacked capacitor structures, the cylindrical structure can utilize not only the outer surface of the cylinder but also the inner surface thereof as an effective capacitor area, so it is adaptable to memory cells of 64 Mb and higher. Currently, another such capacitor structure for increasing the cell capacitance is being suggested by adding a bar or another cylinder in the interior of the cylinder.
The former is disclosed in a paper entitled: "Crown-shaped Stacked-capacitor Cell for 1.5 V Operation 64Mb DRAMs" (Toru Kaga et al., IEEE Electron Devices, Vol. 38, No. 2, pp. 255.about.260, 1991), wherein another cylinder is added in the interior of the cylindrical storage electrodes.
The latter is disclosed in a paper entitled: "A-Stacked Capacitor Cell with Ring Structure" (N. Shinmura et al., 22nd conference on SSDM, Part II, pp. 833.about.836, 1990). Here, a bar is added inside the cylindrical storage electrode, so that the outer and inner surfaces of the cylinder as well as the outer surface of the bar included in the interior of the cylinder can be the effective capacitor area. Thus, the cell capacitance can be increased to the desired extent. However, its manufacturing method and, therefore, mass production are difficult.
FIGS. 1 through 4 are sectional views for illustrating a manufacturing method of a semiconductor memory device presented by Toru Kaga et al., which particularly, in a method for manufacturing a DRAM, relate to a method for forming a capacitor on a structure having a transistor being a constituent of the memory cell of the DRAM on a semiconductor substrate.
Referring first to FIG. 1, a typical manufacturing process of a DRAM before forming its capacitor will be described below.
An active region is separated from an isolation region 101 field oxide layer 101 on a semiconductor substrate 100 by means of a common isolation method, e.g., LOCal Oxidation of Silicon (LOCOS). Successively, transistors having a source region 4 and a gate electrode 2 and commonly shared bit line 6 and drain region 5 are formed on the active region, using common semiconductor manufacturing methods such as deposition, photolithography, and ion-implantation. Thereafter, on the surface of the resultant structure, an insulating layer 8 for insulating each transistor from other conductive layers (to be formed later) is formed. Then, a planarizing layer 10 composed of an insulating material is formed on the surface of the resultant structure.
FIG. 1 is a sectional view showing a step of forming a portion of the storage electrode of the capacitor on the structure having elements up to planarizing layer 10. In more detail, insulating layer 8 and planarizing layer 10 stacked on source region 4 of the transistor are partially removed to thereby form a contact hole. Successively, the contact hole is filled with a first polycrystalline silicon to thus form a bar electrode 16. Then, a first silicon dioxide layer 12, a silicon nitride layer 14, and a second silicon dioxide layer 18 are sequentially stacked. Thereafter, the stacked second silicon dioxide layer 18, silicon nitride layer 14 and first silicon dioxide layer 12 are consecutively etched back to define each memory cell unit and expose a surface of bar electrode 16 so that a well is formed. A material for forming the storage electrode, e.g., a polycrystalline silicon, is deposited on the whole surface of the resultant structure, thereby forming a second polycrystalline silicon layer 20. Also, a third silicon dioxide layer is deposited on second polycrystalline silicon layer 20 and then is anisotropically etched to form a spacer 22 on the sidewall of second polycrystalline silicon layer 20 inside each well.
Referring to FIG. 2, on the surface of the semiconductor substrate having second polycrystalline silicon layer 20 and the spacer 22, a material for forming the storage electrode together with second polycrystalline silicon layer 20, (e.g., a polycrystalline silicon), is deposited to thereby form third polycrystalline silicon layer 24. Thereafter, a fourth silicon dioxide layer 26 is formed on the whole surface of the resultant structure, to cover the surface of third polycrystalline silicon layer 24.
Referring to FIG. 3, fourth silicon dioxide layer 26 is etched back to approximately the height of the peak surface of spacer 22, such that fourth silicon dioxide layer 26 is partially removed. Then, third polycrystalline silicon layer 24 having the exposed surface is removed by means of an anisotropic etching, until the surface of second polycrystalline silicon layer 20 is exposed. Thereafter, second and third polycrystalline silicon layers 20 and 24 whose tops are exposed by means of the anisotropic etching are further anisotropically etched until second polycrystalline silicon layer 18 is exposed, thereby forming a storage electrode 28 of the capacitor. At this time, storage electrode 28 has a larger cylinder formed from second polycrystalline silicon layer 20 and a smaller cylinder formed from third polycrystalline silicon layer 24 within the interior of the larger cylinder on bar electrode 16 formed from the first polycrystalline silicon layer.
Referring to FIG. 4, fourth silicon dioxide layer 26, spacer 22 and second dioxide layer 18 which remain on the resultant structure are eliminated to thereby expose the surfaces of storage electrode 28 of the capacitor. Next, a dielectric film 30 is formed on the whole surface of storage electrode 28, and a fourth polycrystalline silicon is deposited thereon to form a plate electrode 32 of the capacitor, thereby completing the capacitor structure of the DRAM.
According to the conventional method for manufacturing the above-described semiconductor memory device, the storage electrode of the capacitor has another cylinder within a cylinder, so that the effective surface area can be increased, which in turn increases cell capacitance. However, there are several problems with this method.
First, when the first polycrystalline silicon fills up a contact hole for the bar electrode (16 in FIG. 1) formation, the shape of the cylinder formed on the polycrystalline silicon is influenced by the state of the filling of the first polycrystalline silicon. Therefore, it is important to accurately fill the first polycrystalline silicon, (i.e., in the contact hole portion only), but this process is too difficult to be carried out with assurance.
Second, during the step for anisotropically etching second silicon dioxide layer 18, silicon nitride layer 14 and first silicon dioxide layer 12 in order to form the well (the portion formed by partially eliminating the first silicon dioxide layer, silicon nitride layer and second silicon dioxide layer in FIG. 1) for defining the storage electrode, a slope of the sidewall of the well is apt to be negative (namely, the amount of material etched in the surface region of the sidewall is smaller than that being etched in the bottom), so that voids are created between the storage electrode and the plate electrode when forming the plate electrode. Thus, the electrical characteristics of the memory device are diminished.
Third, since the degree of etching is difficult to adjust when etching back fourth silicon dioxide 26 (refer to FIG. 3 and corresponding description), the effective surface area of the storage electrode varies according to the amount of etching so that it is difficult to obtain uniform cell capacitance.
Fourth, when forming third polycrystalline silicon layer 24 after forming second polycrystalline silicon layer 20 (refer to FIG. 2 and corresponding description), a thin natural oxide layer forms on the second polycrystalline silicon layer 20, which also degrades the electrical characteristics of the memory device.
Fifth, the tops of the cylindrical electrode are sharply formed, so that leakage currents are possible.
Sixth, the manufacturing cost is raised due to an overly complicated manufacturing process.